Udemy - Verilog HDL programming with practical approach

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[ DevCourseWeb.com ] Udemy - Verilog HDL programming with practical approach
  • Get Bonus Downloads Here.url (0.2 KB)
    • ~Get Your Files Here ! 01 - Introduction to the course
    • 001 Preview.mp4 (84.6 MB)
    • 001 Preview_en.vtt (15.0 KB)
    • 002 Sample program on edaplayground.mp4 (87.8 MB)
    • 002 Sample program on edaplayground_en.vtt (13.1 KB)
    02 - Introduction to Verilog HDL
    • 001 Verilog fundamentals.mp4 (165.6 MB)
    • 001 Verilog fundamentals_en.vtt (30.0 KB)
    03 - VLSI design flow ( FPGA & ASIC)
    • 001 VLSI Design flow (FPGA & ASIC).mp4 (76.5 MB)
    • 001 VLSI Design flow (FPGA & ASIC)_en.vtt (14.3 KB)
    • 002 FPGA vs ASIC.mp4 (80.1 MB)
    • 002 FPGA vs ASIC_en.vtt (8.7 KB)
    04 - Three levels of verilog design Description
    • 001 Three levels of verilog design Description.mp4 (32.9 MB)
    • 001 Three levels of verilog design Description_en.vtt (3.7 KB)
    • 002 Example mux_2x1 with 3 abstracts models.mp4 (9.1 MB)
    • 002 Example mux_2x1 with 3 abstracts models_en.vtt (1.8 KB)
    05 - Verilog Language constructs, Data types & Compiler Directives
    • 001 Language constructs -Comments, keywords, identifier, Number specific, Operators.mp4 (14.5 MB)
    • 001 Language constructs -Comments, keywords, identifier, Number specific, Operators_en.vtt (2.2 KB)
    • 002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory.mp4 (17.8 MB)
    • 002 Datatypes - net,reg, integer, real, string, time, Parameter, Vector,Array,Memory_en.vtt (3.0 KB)
    • 003 Compiler Directives.mp4 (15.9 MB)
    • 003 Compiler Directives_en.vtt (2.0 KB)
    06 - Verilog Program structure
    • 001 Verilog Program Structure -Module.mp4 (7.4 MB)
    • 001 Verilog Program Structure -Module_en.vtt (1.1 KB)
    • 002 Ports.mp4 (10.7 MB)
    • 002 Ports_en.vtt (1.8 KB)
    • 003 Port Connection Rules.mp4 (13.0 MB)
    • 003 Port Connection Rules_en.vtt (1.9 KB)
    • 004 Design Methodologies Approaches.mp4 (4.7 MB)
    • 004 Design Methodologies Approaches_en.vtt (0.8 KB)
    07 - Gate level modeling
    • 001 Gate Level Model Introduction.mp4 (3.4 MB)
    • 001 Gate Level Model Introduction_en.vtt (0.6 KB)
    • 002 Example 4x1 Mux.mp4 (5.4 MB)
    • 002 Example 4x1 Mux_en.vtt (0.9 KB)
    • 003 Example Full Adder.mp4 (3.6 MB)
    • 003 Example Full Adder_en.vtt (0.7 KB)
    • 004 Tri-state Buffers with Examples.mp4 (12.9 MB)
    • 004 Tri-state Buffers with Examples_en.vtt (2.0 KB)
    • 005 Array of Instance with example.mp4 (10.7 MB)
    • 005 Array of Instance with example_en.vtt (1.6 KB)
    08 - Data flow modeling
    • 001 Data flow Modeling assign statement.mp4 (12.9 MB)
    • 001 Data flow Modeling assign statement_en.vtt (2.3 KB)
    • 002 Operators.mp4 (17.2 MB)
    • 002 Operators_en.vtt (1.9 KB)
    • 003 Arithmetic Operators.mp4 (8.5 MB)
    • 003 Arithmetic Operators_en.vtt (1.4 KB)
    • 004 Logical Operators.mp4 (12.7 MB)
    • 004 Logical Operators_en.vtt (1.6 KB)
    • 005 Example Full Adder Logical operators.mp4 (3.8 MB)
    • 005 Example Full Adder Logical operators_en.vtt (0.8 KB)
    • 006 Example Full Adder Arithmetic operators.mp4 (2.8 MB)
    • 006 Example Full Adder Arithmetic operators_en.vtt (0.8 KB)
    • 007 Example Binary to Gray code converter.mp4 (4.6 MB)
    • 007 Example Binary to Gray code converter_en.vtt (0.9 KB)
    • 008 Logical and , Logical or (&&, ).mp4 (5.6 MB)
    • 008 Logical and , Logical or (&&, )_en.vtt (1.4 KB)
    • 009 Shift operators Leftright Shift.mp4 (17.9 MB)
    • 009 Shift operators Leftright Shift_en.vtt (2.3 KB)
    • 010 Shifting without shift operator , just with concatenation operator.mp4 (4.3 MB)
    • 010 Shifting without shift operator , just with concatenation operator_en.vtt (1.3 KB)
    • 011 Ternary operator Example 2x1 MUX, 4x1 MUX.mp4 (13.6 MB)
    • 011 Ternary operator Example 2x1 MUX, 4x1 MUX_en.vtt (3.2 KB)
    • 012 Relational operators Example Comparator.mp4 (4.5 MB)
    • 012 Relational operators Example Comparator_en.vtt (0.8 KB)
    • 013 Equality (==) , case Equality (===) operators.mp4 (7.1 MB)
    • 013 Equality (==) , case Equality (===) operators_en.vtt (1.9 KB)
    • 014 Reduction operator Example Parity Generator.mp4 (7.1 MB)
    • 014 Reduction operator Example Parity Generator_en.vtt (1.3 KB)
    • 38061230-arthm1.mp4 (3.8 MB)
    09 - Behavioral Modeling
    • 001 Behavioral Modeling - Introduction.mp4 (67.0 MB)
    • 001 Behavioral Modeling - Introduction_en.vtt (7.8 KB)
    • 002 Behavioral Modeling Constructs.mp4 (15.4 MB)
    • 002 Behavioral Modeling Constructs_en.vtt (1.8 KB)
    • 003 Procedural Blocks- initial & always.mp4 (61.1 MB)
    • 003 Procedural Blocks- initial & always_en.vtt (7.6 KB)
    • 004 Example Clock Generation.mp4 (8.4 MB)
    • 004 Example Clock Generation_en.vtt (2.1 KB)
    • 005 Assignment Statements - Blocking & Non-blocking.mp4 (63.3 MB)
    • 005 Assignment Statements - Blocking & Non-blocking_en.vtt (7.0 KB)
    • 006 Mechanism in Non-blocking.mp4 (4.4 MB)
    • 006 Mechanism in Non-blocking_en.vtt (1.2 KB)
    • 007 Concurrency.mp4 (6.4 MB)
    • 007 Concurrency_en.vtt (1.2 KB)
    • 008 Advantage of Non-blocking assignment Example swapping.mp4 (10.2 MB)
    • 008 Advantage of Non-blocking assignment Example swapping_en.vtt (1.4 KB)
    • 009 Advantage of Non-blocking assignment Example Pipelining.mp4 (38.4 MB)
    • 009 Advantage of Non-blocking assignment Example Pipelining_en.vtt (5.6 KB)
    • 010 if-else statement Example 4x1 Mux.mp4 (30.4 MB)
    • 010 if-else statement Example 4x1 Mux_en.vtt (4.3 KB)
    • 011 Case – statement Example 4x1 Mux.mp4 (34.1 MB)
    • 011 Case – statement Example 4x1 Mux_en.vtt (3.6 KB)
    • 012 Advantage of Case over if-else.mp4 (8.0 MB)
    • 012 Advantage of Case over if-else_en.vtt (1.0 KB)
    • 013 Loops while, for

Description

Verilog HDL programming with practical approach



https://DevCourseWeb.com

MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 2.82 GB | Duration: 6h 47m

Fundamentals, levels of design description, Datatypes, test benchs, Tasks & system tasks, FSM with examples & Projects

What you'll learn
Learning Verilog HDL Programming fundamental concepts and properties compare to C Language, feature & advantages of Verilog HDL over VHDL
VLSI Design flow ( FPGA & ASIC) and Difference between FPGA vs ASIC
Different design methodologies in Verilog HDL programming with examples
Behavioral modeling with blocking & Non-Blocking concepts and real time examples
Test bench Verilog program with examples
Task & system tasks with examples for random data generator, file based operations and memory load operations, and file representation input & output etc.
Finite state machine (FSM) with example for both Mealy & Moore and Sequence detector FSM
Complete design & test bench programming for Memory controllers
Complete design & test bench programming for FIFO controller
Complete design & test bench programming for Encoder & decoder for Hamming code Error detection correction
Basics of FPGA
Requirements
Intension to learn
basic in C Language
basics in Digital design ( not compulsory)
Description
Complete Verilog HDL programming course with a perfect, well structured and concise course for freshers and experienced, as it is from fundamental level to the application level. This course discuss the concepts in Verilog HDL programming and properties compared with C-Language and discussing the features and advantages.

In this course we give information related to VLSI design flow for FPGA & ASIC and gives overview about both.



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seeders:6
leechers:4
Udemy - Verilog HDL programming with practical approach
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