Udemy - UART Design and Simulation using Verilog HDL programming

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[ CourseMega.com ] Udemy - UART Design and Simulation using Verilog HDL programming
  • Get Bonus Downloads Here.url (0.2 KB)
    • ~Get Your Files Here ! 01 - Introduction
    • 001 Preview.mp4 (27.1 MB)
    • 001 Preview_en.vtt (4.5 KB)
    • 002 Introduction to Serial Communication.mp4 (6.2 MB)
    • 002 Introduction to Serial Communication_en.vtt (1.1 KB)
    • 003 Limitations of parallel communication and Advantage of Serial communication.mp4 (24.2 MB)
    • 003 Limitations of parallel communication and Advantage of Serial communication_en.vtt (2.8 KB)
    • 004 Synchronous & Asynchronous Serial communication.mp4 (5.8 MB)
    • 004 Synchronous & Asynchronous Serial communication_en.vtt (0.9 KB)
    02 - Introduction to UART
    • 001 What is UART.mp4 (6.9 MB)
    • 001 What is UART_en.vtt (1.4 KB)
    • 002 Data format of UART.mp4 (3.3 MB)
    • 002 Data format of UART_en.vtt (0.6 KB)
    • 003 Transmission & Reception operations in UART.mp4 (29.8 MB)
    • 003 Transmission & Reception operations in UART_en.vtt (4.8 KB)
    • 004 Block diagram for UART.mp4 (10.4 MB)
    • 004 Block diagram for UART_en.vtt (2.8 KB)
    03 - Implementation of UART modules
    • 001 Baud rate generator.mp4 (11.7 MB)
    • 001 Baud rate generator_en.vtt (2.1 KB)
    • 002 Verilog HDL for Baud rate generator.mp4 (93.2 MB)
    • 002 Verilog HDL for Baud rate generator_en.vtt (10.3 KB)
    • 003 FSM for UART Transmitter.mp4 (6.7 MB)
    • 003 FSM for UART Transmitter_en.vtt (1.4 KB)
    • 004 FSM for UART Receiver.mp4 (5.5 MB)
    • 004 FSM for UART Receiver_en.vtt (1.2 KB)
    • 005 Test bench environment.mp4 (22.1 MB)
    • 005 Test bench environment_en.vtt (3.5 KB)
    • 006 Hands on Verilog HDL for UART Transmitter with its Test Bench.mp4 (531.4 MB)
    • 006 Hands on Verilog HDL for UART Transmitter with its Test Bench_en.vtt (45.6 KB)
    • 007 Hands on Verilog HDL for UART Receiver with its Test Bench.mp4 (326.3 MB)
    • 007 Hands on Verilog HDL for UART Receiver with its Test Bench_en.vtt (28.2 KB)
    • 008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB.mp4 (251.4 MB)
    • 008 Hands on Added Logic for sample ticks in Verilog HDL for UART Receiver with TB_en.vtt (25.9 KB)
    • Bonus Resources.txt (0.4 KB)

Description

UART Design and Simulation using Verilog HDL programming



https://CourseMega.com

Genre: eLearning | MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 1.33 GB | Duration: 16 lectures • 2h 50m

Understanding of UART modules and designing UART using Verilog HDL programming

What you'll learn
Serial Communication advantages
UART Fundamentals
Design of UART using Verilog HDL programming
Simulation of UART using Verilog HDL programming

Requirements
Verilog HDL programming
Basic Digital Design
Description
UART Design and Simulation using Verilog HDL course is a well structured and clear understanding and without any confusion about UART protocol and it gives Fundamentals of UART and importance of Serial communication like how it is advantage over parallel communication. Understanding of UART functionality and internal modules and how transfer operation takes place in UART.



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Udemy - UART Design and Simulation using Verilog HDL programming
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