Udemy - High-Level Synthesis For Fpga, Part 3 - Advanced

High-Level Synthesis For Fpga, Part 3 - Advanced



https://DevCourseWeb.com

Published 1/2023
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English | Size: 3.73 GB | Duration: 7h 33m

Logic Design with Vitis-HLS

What you'll learn
Using Multi-Cycle design flow to develop sequential circuits in HLS.
Implementing stream communication and computation in HLS
Using FIFO as the synchronisation mechanism between to connected module
Learning how to use an array variable inside an HLS code
Connecting and AND HLS IP to BRAMs in a Vivado project
Working with pointers in HLS
Working with AXI protocol in HLS
Loop pipelining optimisation in HLS
Loop unrolling optimisation in HLS
Loop flattening optimisation in HLS
Loop rewinding optimisation in HLS
Working with the HLS-Stream library in HLS
Handshaking protocol and interfaces in HLS

Requirements
Understanding the basic concepts of C/C++ coding
Understanding the basic concepts of logic operators (e.g., AND, OR, XOR, SHIFT )
“High-Level Synthesis for FPGA, Part 1-Combinational Circuits” Udemy course
“High-Level Synthesis for FPGA, Part 2 - Sequential Circuits” Udemy course
BASYS3 evaluation board
Xilinx Vitis-HLS and Vivado (download Vivado ML Edition or Vivado Design Suite - HLx Editions for Windows or Linux)